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Dev-Dep Development Contamination Standards

Wafer Contamination StandardsSolutions developed to meet your deposition services needs. Learn more.

Dev-Dep™ Development Contamination Standards from MSP, a Division of TSI, are totally customized to suit the unique and challenging requirements of your inspection or metrology application, with support from MSP's particle deposition experts.


Developing Defect Inspection Equipment

Characterize and optimize the sensitivity and overall performance of the wafer and reticle defect inspection tools you develop using Dev-Dep™ Development Wafer and Reticle Contamination Standards. These certified standards for wafer and reticle inspection tools are made to your specifications with quick turnaround, enabling short learning cycles and accelerating time to market.

Fabricating Electronic Devices

Characterize the performance of inspection/metrology tools and develop inspection protocols for advanced fab process control (APC) of future manufacturing processes. Accurate standards ensure that inspection tools can be used to their full potential so you can maximize device yield.

Download our Wafer and Photomask Surface Defect Contamination Standards Brochure to learn how MSP can help improve your surface defect inspection!


MSP's Dev-Dep™ Development Contamination Standards are built to order from an extensive à la carte menu of substrate base items (substrate with one deposit) and additional deposits.

Each deposit has the following customizable attributes:

  • Deposit Pattern Type
  • Deposit Size and Position
  • Particle Material
  • Particle Size
  • Particle Count



Deposits can be made on a variety of substrates including wafers, reticles (photomasks), and pellicles. Customers typically provide the reticle of their choice, but MSP also provides optical photomask blanks. MSP typically provides bare silicon wafers for deposition but will also process customer-provided wafers with films, patterns, or other proprietary specifications.

Substrate Type MSP-Supplied Substrate Sizes Customer-Supplied Substrate Sizes
Bare Silicon Wafer 200 mm, 300 mm 100 mm*, 150 mm*, 200 mm, 300 mm
Glass Wafer 200 mm*, 300 mm* 100 mm*, 150 mm*, 200 mm*, 300 mm*
Sapphire Wafer 100 mm*, 150 mm*, 200 mm* 100 mm*, 150 mm*, 200 mm*
SiC Wafer N/A 100 mm*, 150 mm*
GaAs Wafer N/A 100 mm*, 150 mm*
Film or Patterned Wafer N/A 100 mm*, 150 mm*, 200 mm, 300 mm
Optical Reticle (Photomask) 6 inch x 6 inch x 1/4 inch (Blank Only) 6 inch x 6 inch x 1/4 inch (All Types)
EUV Reticle (Photomask) N/A 6 inch x 6 inch x 1/4 inch (All Types)
Pellicle N/A TBD*

* Non-standard substrate, processing of which may be subject to additional fees.


Each deposit can be customized with a number of attributes from the selections listed in the following table. Restrictions apply to some combinations of attribute selections.

Attribute Available Options or Ranges
Pattern Type Spot, Full, Arc*, Ring*
Particle Type / Material

+ PSL Spheres (Size Standards)
+ SiO2 Spheres (including MSP NanoSilica™ Size Standards)
+ MSP Process Particles™ Suspensions (AlF3, Al2O3, Ni, Ru, Si, Si3N4, SiO2, Sn, Ta, Ti, TiN, TiO2, W, Y2O3)

Particle Size 10 nm – 20 μm**
Particle Count Minimum 100 particles per deposit
Pattern Width Typically 10-30 mm; Range of Pattern Width (e.g., Spot Diameter) is dependent on Particle Size
Pattern Location Substrate-dependent

* Non-standard patterns, processing of which may be subject to additional fees.
** All-inclusive particle size range. Restrictions apply to each particle type/material.

Dev-Dep Development Reticle Contamination Standards

Reticle/photomask contamination standards consist of particles deposited on 6 inch reticles...

Dev-Dep Development Wafer Contamination Standards

Wafer contamination standards consist of particles deposited on a wafer (sizes from 100 mm to...

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